DAC: Cadence builds its cloud-based design world

Cadence Design Systems announces a cloud-based chip and system design tool portfolio which has both Cadence-managed and customer-managed environments.

It brings the scalability of the cloud into play for developers allowing them to securely manage high complexity designs, with  scalable compute resources available in minutes or hours instead of months or weeks.

The announcement was made this week at the Design Automation Conference (DAC) being held in San Francisco (June 25-28). 

Cadence says it has already hosted design environments for more than 100 customers of varying sizes.

 “The cloud will fundamentally influence silicon design by giving semiconductor companies the ability to optimise their capital versus operational expenses for computing infrastructure,” said Suk Lee, senior director at TSMC. 

Cadence’s cloud-based tool portfolio includes support for customers who establish and manage their own IT and business relationships with Amazon Web Services (AWS), Google Cloud Platform (GCP) or Microsoft Azure. 

The firm offers cloud-ready software tools that have been tested for use in the cloud. 

These include tools for circuit simulation, power and EM analysis, logic simulation, formal verification, physical verification, timing sign-off, extraction, power integrity and library characterisation.

Cadence can manage cloud-based design environments for users offering tools in a design environment built on AWS or Microsoft Azure that has been customised for company-specific infrastructure requirements. 

This is accessed through a portal developed by Cadence.  

The attraction of the cloud for start-ups and small companies is that it reduces the need for capital infrastructure investments and IT expenses.

Cadence also supports its Palladium emulator through the cloud. Customers purchase gate capacity, which is used when needed.  

Dr. Anirudh Devgan, president of Cadence, writes:

“We’ve delivered the Cadence Cloud portfolio to address the challenges our customers face—the unsustainable peak compute needs created by complex chip designs and exponentially increasing design data.”  

Source from:electronicsweekly